Mixed Signal Verification Engineer

Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Our design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.

We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite position

Job Responsibilities:

• Creating AMS/DMS testbench for wireless RF and High Speed PHY.
• Working with RF/Analog design engineers for analog circuit models
• Support silicon bring-up and commercialization.

Required Skills:

• BS or BE minimum, 3+ year experiences
• Deep understanding of digital VLSI simulation flow
• Deep understanding of mixed-mode and analog simulation flow
• Experience with Verilog/SystemVerilog and RNM modeling
• Experience with digital verification, UVM, and waveform debug
• Teamwork, dedication, strong communications and interpersonal skills
• Excellent communication skills both written and verbal PREFERED SKILLS
• Deep understanding of wireless RF transceiver and Serdes PHY technology

Thanks & Regards

Divakar Dhandapani