Staff Engineer – CPU / ASIC / Physical Design

Staff Engineer – CPU / ASIC / Physical Design

Location: San Diego, CA

Experience: 4–10 years

Job Description:

Looking for a Staff Engineer with strong experience in CPU/SoC design, RTL development, ASIC, and/or Physical Design. Candidates should have hands-on experience with Verilog/SystemVerilog, digital design, synthesis, timing closure, PPA optimization, and ASIC/SoC development flows.

Must-Have Skills:

• 4–10 years in ASIC/SoC, CPU, RTL, or Physical Design
• Verilog/SystemVerilog
• CPU/microarchitecture or digital design knowledge
• Synthesis / STA / Timing Closure / PPA optimization
• RTL-to-GDSII or Physical Design experience is a strong plus
• Cadence Innovus / Synopsys Fusion Compiler / PrimeTime preferred
• Linux/Unix
• Python, Tcl, Perl, or Shell scripting
• Experience with MMMC, CDC, lint, ECOs, power/area/timing optimization preferred

Good target titles for sourcing:

• Staff ASIC Design Engineer
• CPU Design Engineer
• CPU RTL Design Engineer
• ASIC Design Engineer
• SoC Design Engineer
• RTL Design Engineer
• Physical Design Engineer
• ASIC Physical Design Engineer
• CPU Microarchitecture Engineer
• RTL-to-GDS Engineer
• Timing/STA Engineer
• PPA Optimization Engineer