Principal / Senior Principal Logic Design Engineer – PCIe, RTL, ASIC/FPGA

Location: San Jose, CA

Work Arrangement: Hybrid – 3 days onsite / 2 days remote per week, with flexibility on which days are worked onsite. Candidates must be able to work onsite in San Jose 3 days per week.

KORE1, a nationwide provider of staffing and recruiting solutions, has an immediate opening for a Principal / Senior Principal Logic Design Engineer – PCIe, RTL, ASIC/FPGA.

Compensation depends on experience but is typically $127,400 - $287,000/yr.

KORE1, a nationwide provider of staffing and recruiting solutions, has an immediate opening for a Principal / Senior Principal Logic Design Engineer – PCIe, RTL, ASIC/FPGA.

We are seeking an exceptional Principal or Senior Principal Logic Design Engineer to join a Silicon IP (SIP) team in San Jose, California. The position may be hired at either the Principal or Senior Principal level based on the candidate's experience and technical depth, with Senior Principal preferred.

Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

In this role, the candidate will report to the Director of Engineering as an individual contributor. As a Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of next-generation, high-performance, cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers, providing ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you.

At the Senior Principal level, this individual will also be expected to provide technical leadership and mentorship to other engineers while remaining an individual contributor.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data
• Collaborate closely with the verification team to shape test plans and improve verification coverage
• Work with the physical design team to understand and resolve timing, power, and congestion challenges
• Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary
• Provide technical support to the FAE team on pre-sales customer engagements
• Provide technical support to the AE team on post-sales customer deliveries
• Apply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow
• Develop RTL micro-architecture from scratch
• At the Senior Principal level, provide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor

Qualifications

• 8+ years of directly relevant logic design experience (ASIC and/or FPGA) with an MSEE, or 10+ years with a BSEE; MSEE preferred
• Demonstrated technical scope appropriate for a Principal or Senior Principal-level individual contributor
• Strong SystemVerilog/Verilog RTL design and coding experience
• Direct PCIe logic design experience required
• Demonstrated experience developing RTL/micro-architecture from scratch
• Working knowledge of CDC/RDC
• Questa/Incisive/VCS simulator experience
• Python/Perl/TCL scripting experience
• Ability to learn quickly and work independently
• Strong communication, technical leadership, and project management skills
• Must be able to work onsite in San Jose, CA 3 days per week
• Authorization to work in the United States required (USC, Green Card, or H-1B; approved I-140 preferred)

Definite Plus

• Memory or memory-controller design experience, including HBM or LPDDR; PCIe memory-controller experience is a strong plus
• ASIC synthesis and timing-constraint experience
• UVM verification experience
• AMBA AXI or CHI design experience

Compensation & Benefits

Compensation depends on experience and level. The San Jose, CA base salary range is $127,000–$287,600/year, with offers generally targeted around the midpoint of the applicable range based on level and experience.

The position also includes:

• Annual bonus based on level:
• Senior Principal: 20%
• Principal: 15%
• RSUs, tiered by title, with 4-year vesting and a 1-year cliff
• 401(k) with 3% company match, immediately vested
• Unlimited PTO
• Approximately 6 additional company-wide Fridays off per year